The present invention relates to a current limiter for switching devices. In particular the invention is applicable to current protection stages of switching power supplies or, more in general, to other switching systems for driving inductive loads.
Devices of this kind generally comprises a drive stage feeding a power transistor which in turn feeds a load which comprises a filter including at least one inductive element. A current sensor system is furthermore connected to the power transistor (of the bipolar or MOSFET type), to evaluate the current flowing in the load and to send an error signal if said current exceeds a preset threshold.
In order to achieve a current limitation of the output stage with impulse by impulse operation, it is possible to provide a current limiter connected downstream of the sensor and generating a disabling signal for interrupting load feeding following reception of the overload signal supplied by the sensor.
A known circuit which operates in the manner described is indicatively illustrated in FIG. 1, while FIG. 2 depicts a number of waveforms related to different points of the known circuit. In FIG. 1, the reference numeral 10 indicates the drive stage of a known type for a switching power supply, the drive stage feeding the base of a power transistor 11. In the example illustrated, the emitter of the transistor 11 is connected to an output filter circuit, comprising an inductor 12, a capacitor 13, a resistor 14, and a diode 15, while the collector of the transistor 11 is connected to the supply voltage V.sub.CC through a control resistor R.sub.S' 16, which constitutes a current sensor and generates a voltage signal proportional to the current flowing in the load. This voltage signal is supplied on the input 19 of a comparator 17, the other input of which (indicated with the reference numeral 18) is connected to a reference voltage, here the power supply voltage. The output 20 of the comparator is supplied to an input 22 of a bistable memory element 21 (here a flip-flop of the set-reset type) to the reset type 23 of which is applied a main clock signal MC1 which constitutes the general switching frequency of the system. The main output Q, 24 of the memory element 21 is then sent to an enabling input of the drive stage 10 so as to inhibit its operation upon receiving an overload signal from the sensor circuit and to re-enable the drive stage 10 upon the reception of the impulses of the main clock signal on the input 23. For the sake of greater clarity, FIG. 2 illustrates waveforms related to points of the circuit of FIG. 1. In particular, FIG. 2 a illustrates the main clock signal applied to the reset input of the flip-flop 21, FIG. 2b illustrates the current flowing through the transistor 11 and indicated with I.sub.TR, while FIG. 2c illustrates the load current I.sub.L. As can be seen, after the arrival of a reset impulse through the input 23 and the output 24 (with a slight delay due to he propagation times of the current I.sub.TR towards the load. When this current, which has a very short rise time, reaches the desired limit threshold value I.sub.M', the voltage values on the inputs 18 and 19 of the comparator 17 will be such as to generate a switching off signal on the output 20, which signal is then fed on the set input of the flip-flop 21, causing the latter to switch. Then the flip-flop 21 generates an inhibiting signal on the output 24 which switches off the drive signal 10 and the transistor 11 until the arrival of the successive impulse of the main clock on the reset input 23. As a consequence, the flip-flop 21 switches again, supplying the stage 10 with an enable signal and allowing therefore load feeding. In practice, the load will show the current behaviour illustrated in FIG. 2c by virtue of the action of the filter components 12, 13 which maintain an average current and voltage value on the load. In practice, the device, when in overload conditions, acts as a current source.
However, the circuit described, which in all other ways operates reliably, is characterized by inadequate functioning due to the delay times related to the propagation of the signals from the sensor stage to the actuator stage. Indeed, it is intuitively understood that if the propagation delay of the overload signal if percentually high with respect to the period of the main clock signal, there will not be an adequate current limitation. In particular, the propagation delay determines the minimum duration of the current impulse which the system is capable of adjusting when in protection mode. This delay time is all the more critical as the switching frequency or clock frequency of the circuit is high, since, in order to determine the output current, the duty cycle, i.e. the ratio between the switching-on time T.sub.ON of the transistor and the period T of the main clock, is fundamental.